ADSP-SC583 datasheet, dsp equivalent, Analog Devices

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Features and benefits

Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional abili.

Application

SYSTEM CONTROL SECURITY AND PROTECTION SYSTEM PROTECTION (SPU) SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT Ar.

Description

......... 3 Arm Cortex-A5 Processor ......... 5 SHARC Processor ......... 6 SHARC+ Core Architecture ...... 8 System Infrastructure ... 10 System Memory Map ... 11 Security Features ........ 14 Security Features Disclaimer .... 15 Safety Features . 1.

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